Design of a New SEU-tolerant SRAM Cell Structure

In accelerator particle physics experiments, it is a development trend to realize the functions of analog signal processing and digitization at the front end of readout electronics based on application specific integrated circuits(ASICs), but it also exposes ASICs in the radiation environment of high-energy particles, The static random access memory(SRAM) is vulnerable to radiation, resulting in single event upset(SEU), which makes the chip abnormal. Therefore, it is necessary to design radiation-hardened SRAM in those ASICs. In this paper, a SEU-tolerant SRAM memory cell with 11 transistors(11 T) based on Schmitt trigger is proposed. The circuit is designed and simulated in 180 nm CMOS process. The simulation results show that our proposed 11 T SRAM cells as compared with traditional 12 transistors(12 T) SRAM cell have considerably higher robustness against single-event multiple effects, and consumes only 42% power of the 12 T cell.