Design of Peak Holding Circuit in Readout ASIC of PSD

The output signal of PSD(plastic scintillation detector) is fed to the preamplifier and the shaping circuit to output a quasi-Gaussian waveform. The peak holding circuit can be used to sample and hold the peak value of the quasi-Gaussian waveform signal, so that the subsequent electronic system can further analyze it. This paper presents a peak holding circuit ASIC(application specific integrated circuit) chip which is designed based on 180 nm CMOS technology. Each channel of the ASIC includes an OTA(Operational Transconductance Amplifier) circuit, a current mirror circuit, and a charging capacitor. Laboratory electronics function and performance test results indicate that the function of the peak hold circuit is achieved. The input dynamic range is 33~940 mV, and the nonlinear error is better than 0.8%. The droop rate is better than 8.6 μV/μs, the peak detection delay time is lower than 35 ns, and the single-channel power consumption of the chip is 825 μW, which meets the design requirements.