Testing and Evaluation of the DHR TDC ASIC

As one of the key components in high precision time measurement based on discrimination and time digitization, the time-to-digital converter(TDC) is widely used in many fields. This paper presents the design and testing of a DLL based TDC prototype ASIC named DHR TDC with a large detectable range and high resolution in 180 nm CMOS technology. A test module was designed and the test platform was set up for the TDC performance evaluation. Test results indicate that this TDC achieves a time resolution of better than 60 ps RMS with an averaged bin size of around 156 ps, as well as a measurement dynamic range of up to 20 µs, and its differential nonlinearity(DNL) and integral nonlinearity(INL) are better than 0.13 LSB and 0.15 LSB, respectively.