-
The test devices were fabricated using a commercial 14-nm bulk FinFET complementary metal-oxide-semiconductor(CMOS) technology. The capacity of the SRAM array was 128 Mbits. The device’s normal core logic supply voltage was 0.8 V, and the IO voltage was 1.8 V. The clock frequency was adjustable with a 5 MHz minimum value to meet system timing requirements. The area of one memory cell was approximately 0.067 μm2. The information about the device is listed in Table 1.
Paraments Value Technology 14 nm, FinFET CMOS, Flip-Chip Packaged Die area 6.17 mm × 17.87 mm Core voltage/IO voltage 0.8 V/1.8 V Array dimension 128 Mbits Cell area 0.18 μm × 0.37 μm Fin height/Fin width 45 nm/15 nm Fin pitch/Contacted
gate pitch46 nm/85 nm Table 1. Information of the device.
A homemade test system was consisted of a robust mainboard and a replaceable DUT board. The main board receives the request command from the host. Data operations such as write/read/compare/correct were performed to run the DUT. The motherboard use to read the current value of DUT in real time along-with a record of the detected error details. Then, it was being uploaded to the host through Ethernet as the communication port. The mainboard and DUT board can transmit signals and powers by 180 differential pairs- channels through four Samtec’s high-speed connectors. There was no other device placed nearby the irradiation region. The current of the DUT power components was continuously monitored and displayed in real-time. Slight voltage variations were probed and multiplied by a precision resistor and current sense amplifier, which were afterward converted to a digital form that can be handled by an FPGA rely on a 12-bit ADC. The DUT currents were monitored at one-second intervals.
-
The tests of heavy-ion irradiation were performed at the Heavy Ion Research Facility in Lanzhou(HIRFL) and HI-13 Tandem Accelerator in Beijing. Experiments were carried out with different broad beam ion species including 12C, 19F, 78Kr and 86Kr. The heavy ions’ LET at the sensitive volume(SV) surface is range from 2.4 to 40.3 MeV/(mg/cm2). The detailed experimental parameters used in this experiment are provided in Table 2. The heavy ions’ LET values and the projected ranges in silicon were calculated by the Stopping and Range of Ions in Matter (SRIM) software[13]. All tests were conducted at a normal voltage of 0.8 V and room temperature.
Terminal Ion
speciesEnergy*/
MeVLET */
[MeV/(mg·cm–2)]Penetration depth/
range in Si/μmHI-13 12C 52 2.6 67 19F 47 6.3 28 HIRFL 78Kr 3578 12.7 775 2210 17.4 373 86Kr 1371 24.7 185 904 30.6 112 294 40.3 38 *At the surface of SV. Table 2. Parameters of Heavy Ions Used in the Experiment.
Additionally, the 78Kr ions with initial energy 3 751 MeV were carried out at different angles incidence relative to two axes: 30°, 45° and 60°, as shown in Fig. 2(d) and (e). Fig. 2 shows the fin structure and the incident angle relative to the fin structure. The BC axis is parallel to fin direction, and the angle of the DUT around the BC axis is marked as α angle. The AB axis is perpendicular to fin direction, and the angle of the DUT around the AB axis is marked as β angle.
Single-event Upsets (SEUs) Induced by Heavy Ions in 14-nm FinFET SRAM
doi: 10.11804/NuclPhysRev.38.2021015
- Received Date: 2021-02-23
- Rev Recd Date: 2021-03-13
- Available Online: 2021-09-27
- Publish Date: 2021-09-20
-
Key words:
- FinFET SRAM /
- heavy ion /
- single-event upset(SEU) /
- angle effect
Abstract: The characteristic of single-event upset(SEU) in a 14-nm bulk fin field-effect transistor (FinFET) static random access memory(SRAM) is investigated by heavy-ion experiments. The linear energy transfer(LET) threshold 0.1 MeV/(mg/cm2) is obtained by fitting the SEU cross-section using the Weibull function. The contribution of multiple-bit upset(MBU) is investigated. The results show that when the LET is equal to 40.3 MeV/(mg/cm2), greater than 95% of SEU comes from the MBU. Additionally, the SEU cross-section of the FinFET SRAM presents anisotropies for incident angles associated with the fin direction. This research has a certain kind of guiding role in designing of radiation-hardened complementary metal-oxide semiconductor(CMOS) integrated circuits(ICs) based on FinFET technology.
Citation: | Lihua MO, Bing YE, Jie LIU, Zhangang ZHANG, Teng TONG, Youmei SUN, Jie LUO. Single-event Upsets (SEUs) Induced by Heavy Ions in 14-nm FinFET SRAM[J]. Nuclear Physics Review, 2021, 38(3): 327-331. doi: 10.11804/NuclPhysRev.38.2021015 |