Abstract: NICA(Nuclotron-based Ion Collider fAcility) is a heavy ion collider based on superconducting particle accelerator developed by China and Russia. According to the requirements of data receiving and sending in NICA ROC(NICA Readout and Control) ASIC, designed for ITS front-end data collection and transmission in NICA MPD, a Low Voltage Differential Signaling(LVDS) high-speed serial interface circuit is designed as the data interface between NICA ROC and front-end readout ASICs, and the pre-emphasis technique is employed to reduce the inter-symbol interference. Based on 130 nm CMOS technology, the circuit design, simulation, layout design, and tape-out of LVDS receiver and driver have been completed. A test system is designed for this high-speed serial interface chip. The test results show that the LVDS transceiver can achieve 800 Mbps receiving and transmitting data rate, and the differential output voltage is about 260 mV, with the Bit Error Ratio(BER) less than 1 \times 10^-13. The power consumption of a pair of LVDS transceiver is approximately 9.5 mW. This design meets the design requirements of NICA ROC ASIC.