Abstract: In order to sample and process the signal of the Shanghai High Repetition Rate XFEL and Extreme Light Facility (SHINE) strip-line BPM system, a prototype of High-Repetition-Rate Beam Sampling Processor was developed. The processor has four channel input, 1 GSps maximum sampling rate and 16 bit resolution. It adopts Xilinx Zynq series FPGA with embedded ARM core, which can run Linux operating system and realize readout of high-speed sampled-data and data buffering. The processor adopts the structure of mother board and daughter board. The daughter board with ADC is for data sampling, and the mother board with FPGA is used to process the digital data. The daughter board and the mother board transmit data through the FMC interface. The ADC uses JESD204B protocol to transmit data, and the maximum total data rate is 80 Gbps through 16 pairs of differential channels. First the ADC data is transmitted to the digital motherboard. Then it is buffered by FIFO and DDR and finally transmitted to the upper computer for processing and analysis through the RJ45 interface with TCP/IP protocol. The data rate of RJ45 interface is about 900 Mbps. After testing, the bandwidth of ADC daughter board is higher than 480 MHz, and the ENOB(effective number of bits) is higher than 10-bit in 480 MHz bandwidth. The FPGA digital mother board runs Linux compiled by Petalinux, which can realize the data storage and transmission of 1 M sampling points of four channels in continuous or trigger mode. The processor can meet the design requirements.