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12 bit 30 MSPS逐次比较型ADC的测试

杨云帆 赵雷 周圣智 刘建峰 刘树彬 安琪

杨云帆, 赵雷, 周圣智, 刘建峰, 刘树彬, 安琪. 12 bit 30 MSPS逐次比较型ADC的测试[J]. 原子核物理评论, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
引用本文: 杨云帆, 赵雷, 周圣智, 刘建峰, 刘树彬, 安琪. 12 bit 30 MSPS逐次比较型ADC的测试[J]. 原子核物理评论, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
Citation: YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046

12 bit 30 MSPS逐次比较型ADC的测试

doi: 10.11804/NuclPhysRev.35.01.046
基金项目: 国家自然科学基金资助项目(11722545);中国科学院知识创新工程重要方向性项目(KJCX2-YW-N27)
详细信息
    作者简介:

    杨云帆(1993-),男,河南新乡人,硕士研究生;E-mail:yyf1993@mail.ustc.edu.cn

    通讯作者: 赵雷,E-mail:zlei@ustc.edu.cn。
  • 中图分类号: TL503.6

Testing of a 12 bit 30 MSPS SAR ADC

Funds: National Natural Science Foundation of China (11722545); Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27)
More Information
    Corresponding author: ZHAO Lei, E-mail:zlei@ustc.edu.cn。
  • 摘要: 针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器(Analog-to-Digital Converter,ADC)芯片,为评估其性能指标参数,需进行系统的测试。在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析。测试结果表明,输入信号在基带范围内ADC有效位(Effective Number Of Bit,ENOB)约为9 bit,达到了本版本芯片的设计指标。同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据。


    Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.
  • [1] CAO Zhen. Chinese Physics C, 2010. 34(2):249.
    [2] YAO Zhiguo, WU Hanrong, CHEN Mingjun, et al. Proceedings of the 32nd ICRC, 2011.
    [3] ZHAO Lei, LIU Shubin, AN Qi. Chinese Physics C, 2014. 38(1):016101.
    [4] LIU Jianfeng, ZHAO Lei, YU Li, et al. Evaluation of a Frontend ASIC Prototype for the Readout of PMTs in Water Cherenkov Detector Array[C]//IEEE International Conference on Electronic Measurement & Instruments, IEEE, 2016:507.
    [5] LIU Jianfeng, ZHAO Lei, QIN Jiajun, et al. Chinese Physics C, 2016. 40(11):116103.
    [6] SiTime Corporation. SiT91211-220 MHz High Performance Differential Oscillator. Rev 1.07[EB/OL].[2017-01-19]. https://www.sitime.com/products/lvpecl-lvds-hcsloscillators/sit9121.
    [7] Analog Devices, Inc. 12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO, AD9522-3 Data Sheet. Rev. A[EB/OL].[2017-01-19]. http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/ad9522-3.html.
    [8] IEEE Instrumentation & Measurement Society. IEEE Standard for Terminology and Test Methods for Analog-to-digital converters[C]//IEEE Std 1241-2010(Revision of IEEE Std 1241-2000):1.
    [9] LIU Wenbo, HUANG Pingli, CHIU Yun. IEEE Journal of Solid-State Circuits, 2011. 46(11):2661.
    [10] KURAMOCHI Y, MATSUZAWA A, KAWABATA M. A 0.05-mm 2110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS[C]//Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, IEEE, 2007:224.
    [11] MURMANN B. Digitally Assisted Data Converter Design[C]//ESSCIRC (ESSCIRC), 2013 Proceedings of the IEEE, 2013:24.
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出版历程
  • 收稿日期:  2017-05-04
  • 修回日期:  2017-06-02
  • 刊出日期:  2018-03-20

12 bit 30 MSPS逐次比较型ADC的测试

doi: 10.11804/NuclPhysRev.35.01.046
    基金项目:  国家自然科学基金资助项目(11722545);中国科学院知识创新工程重要方向性项目(KJCX2-YW-N27)
    作者简介:

    杨云帆(1993-),男,河南新乡人,硕士研究生;E-mail:yyf1993@mail.ustc.edu.cn

    通讯作者: 赵雷,E-mail:zlei@ustc.edu.cn。
  • 中图分类号: TL503.6

摘要: 针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器(Analog-to-Digital Converter,ADC)芯片,为评估其性能指标参数,需进行系统的测试。在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析。测试结果表明,输入信号在基带范围内ADC有效位(Effective Number Of Bit,ENOB)约为9 bit,达到了本版本芯片的设计指标。同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据。


Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.

English Abstract

杨云帆, 赵雷, 周圣智, 刘建峰, 刘树彬, 安琪. 12 bit 30 MSPS逐次比较型ADC的测试[J]. 原子核物理评论, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
引用本文: 杨云帆, 赵雷, 周圣智, 刘建峰, 刘树彬, 安琪. 12 bit 30 MSPS逐次比较型ADC的测试[J]. 原子核物理评论, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
Citation: YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
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