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采用180 nm 标准商用CMOS工艺在Cadence virtuoso中设计了上述11管单元结构的原理图,并对其进行了噪声容限仿真、SEU仿真和功耗仿真。
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静态噪声容限(SNM)经常被用来衡量SRAM单元的稳定性,特别是写和保持条件下的静态噪声容限[18]。SNM的仿真方法如图8所示,通过在敏感节点插入单端噪声源,来观察Q和Qb节点的电压。经过仿真得到的普通6管单元和11管单元的保持静态噪声容限(HSNM)和写静态噪声容限(WSNM)如图9所示,图中虚线正方形的对角线的长度为SNM的大小。在电源电压1.8 V、tt工艺角和25 ºC条件下,仿真结果表明,11管单元的HSNM为0.68 V,相比6管单元的0.63 V提升了6%。在此条件下,11管单元的WSNM为1.50 V,相比于6管单元的0.70 V有两倍以上的提升。图10展示了在通用NP(tt)、快N快P(ff)、快N慢P(fs)、慢N快P(sf)和慢N慢P(ss)等5种不同工艺角下上述噪声容限仿真结果,可以看到在不同的工艺角下11管单元相比6管单元都有提升,且写噪声容限提升明显。
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为了验证本论文中SRAM单元的抗SEU性能,仿真是必不可少的。这里使用文献[19]中提出的双指数电流注入模型来模拟粒子轰击在器件上所产生的瞬态电流。
$$ \begin{split} \\ I(t) = {\text{ }}{I_0}({{{\rm{e}}}^{ - \alpha t}} - {{{\rm{e}}}^{ - \beta t}}) \text{,} \end{split}$$ (1) 式中:
$ {I_0} $ 为注入电流的大小;$ \alpha $ 和$ \beta $ 为时间常数。对该电流源积分即可得到该节点的注入电荷。由上文可知SRAM单元被高能粒子轰击敏感节点时会沉积大量的电荷,当沉积的电荷足够多时该节点将会发生翻转,而产生翻转所需的最小电荷量叫做临界电荷
$ {Q_{{\text{Cri}}}} $ 。当模拟一个高能粒子轰击敏感节点时,将一个双指数电流源连接到该节点,通过仿真可以得到不同的注入电荷对SRAM敏感节点的影响,并且找到该敏感节点的临界电荷。此外本电路设计采用的CMOS工艺其衬底材料为硅,通过式(2)可以计算出敏感节点收集到的电荷$ {Q_{\text{C}}} $ 对应的粒子LET值[20]:$$ {Q_{C}} = 1.03 \times {10^{ - 2}}{\text{ }}({L_{{\rm th}}} {\boldsymbol{\cdot}} T)\;{{\rm{pC}}} \text{,} $$ (2) 这里
$ {Q_C} $ 的单位是pC;${L_{{\rm th}}}$ 的单位是$ \text{MeV}\cdot \text{c}{\text{m}}^{\text{2}}\text{/mg} $ ;$ T $ 的单位为μm。将双指数电流脉冲在保持状态下注入到11管单元的敏感节点中,其仿真波形如图11所示。表1显示了普通6管单元、11管单元和12管单元各节点临界电荷仿真结果。11管单元相比于6管单元和12管单元造成单粒子翻转所需的临界电荷都有明显提升,并且从1到0翻转和从0到1翻转所需临界电荷有差异。且11管单元是非对称的Q与Qb节点的临界电荷亦不相同。
表 1 SEU仿真结果对比表
节点 翻转 临界电荷/fC LET(MeV·cm2/mg)器件厚度2 μm 6管 Q/Qb 0→1 223.8 10.86 1→0 180.4 8.76 11管 Q 0→1 286.2 13.89 1→0 224.2 10.88 Qb 0→1 1 328.3 64.48 1→0 794.5 38.57 12管 Q 0→1 273.1 13.25 1→0 218.1 10.58 Qb 0→1 891.2 43.26 1→0 509.1 24.71 -
在工作电压为1.8 V,工作频率20 MHz下仿真6管单元、11管单元、将11管单元中MN7管去掉后的10管单元及12管单元的平均功耗,如图12所示。由于11管单元在写操作时会先断开反馈,所以可以看到,加入MN7管后11管单元的功耗节省了37%。并且由于在写0操作过程中12管单元存在电源通过MP1和MP3到地导通的情况,12管单元的功耗是11管单元的2.4倍。图13为11管单元和普通6管单元的版图,其中普通6管单元的面积为4.62 μm ×5.04 μm,11管单元的面积为10.56 μm×5.04 μm。
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摘要: 在加速器粒子物理实验中,基于专用集成电路(Application Specific Integrated Circuit, ASIC)在读出电子学前端实现模拟信号调理、数字化等功能是一个发展趋势,但这也使得ASIC暴露在了高能粒子辐射环境中,而其中的静态随机存储器(Static Random-Access Memory, SRAM)容易受到辐射的影响产生单粒子翻转(Single Event Upset, SEU),从而使芯片工作异常。因此对ASIC中的SRAM进行抗辐照加固设计十分必要。本工作提出了一种基于施密特触发器结构的11管抗SEU SRAM存储单元,并在180 nm CMOS工艺下进行了电路的设计和仿真,仿真结果表明,与传统12管SRAM单元相比,抗单粒子翻转能力有明显增加,且功耗仅为12管单元的42%。Abstract: In accelerator particle physics experiments, it is a development trend to realize the functions of analog signal processing and digitization at the front end of readout electronics based on application specific integrated circuits(ASICs), but it also exposes ASICs in the radiation environment of high-energy particles, The static random access memory(SRAM) is vulnerable to radiation, resulting in single event upset(SEU), which makes the chip abnormal. Therefore, it is necessary to design radiation-hardened SRAM in those ASICs. In this paper, a SEU-tolerant SRAM memory cell with 11 transistors(11 T) based on Schmitt trigger is proposed. The circuit is designed and simulated in 180 nm CMOS process. The simulation results show that our proposed 11 T SRAM cells as compared with traditional 12 transistors(12 T) SRAM cell have considerably higher robustness against single-event multiple effects, and consumes only 42% power of the 12 T cell.
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Key words:
- SRAM cell /
- SEU /
- ASIC /
- radiation resistance
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图 2 基于施密特触发器的12管SRAM结构[10]
表 1 SEU仿真结果对比表
节点 翻转 临界电荷/fC LET(MeV·cm2/mg)器件厚度2 μm 6管 Q/Qb 0→1 223.8 10.86 1→0 180.4 8.76 11管 Q 0→1 286.2 13.89 1→0 224.2 10.88 Qb 0→1 1 328.3 64.48 1→0 794.5 38.57 12管 Q 0→1 273.1 13.25 1→0 218.1 10.58 Qb 0→1 891.2 43.26 1→0 509.1 24.71 -
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