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摘要: 面向全国产化工艺的5 Gbps SerDes(Serializer/DESerializer,串化器/解串器)芯片的需求,设计了其中的20:1 Serializer(并串转换电路)。该并串转换电路基于国产GSMC 130 nm CMOS工艺设计,其内部电路结构设计采用了一级5:1模块和两级2:1模块级联方式,并由多相时钟发生器和分频器提供相应的时钟信号,将20路250 Mbps并行数据转换成1路5 Gbps的高速串行数据进行传输。在温度−40~100 °C、全工艺角环境、电路工作电压在1.08~1.32 V 的条件下,后仿真结果均显示该电路功能正确,能输出完整清晰的5 Gbps数据眼图, 满足设计需求。 其中在27 °C、TT Corner(典型值工艺角)、1.2 V工作电压条件下仿真结果表明该并串转换电路整体总功耗为39.12 mW、总抖动为8.34 ps、输出电压满摆幅为800 mV。Abstract: This paper designs a 20:1 Serializer for a 5 Gbps SerDes (Serializer/DESerializer) ASIC fabricated using China's domestic GSMC 130 nm CMOS process. This Serializer converts the 20-bit 250 Mbps parallel data into 1-bit 5Gbps serial data. It consists of one stage of 5:1 conversion module and two stages of 2:1 conversion module. The clocks are provided by a multi-phase clock generator and a frequency divider. Post-simulations with all process corners, the temperature is from −40 °C to 100 °C and supply voltage is from 1.08 to 1.32 Volt, show this Serializer functions correctly and can generate a clear eye diagram at 5 Gbps, which fulfills the design requirements. Mainly, simulation with the typical process corner, the temperature at 27 °C, and supply voltage at 1.2 Volt show that the total power dissipation is 39.12 mW, the total jitter is 8.34 ps, and the output voltage rail-to-rail is 800 mV.
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[1] 王伟涛. 8b/10b架构SerDes芯片的设计与实现[D]. 成都: 电子科技大学, 2016(5): 5. WANG Weitao. Design and Implementation of SERDES Chip Based on 8b/10b Architecture[D]. Chengdu:University of Electronic Science and Technology of China, 2016(5): 5. (in Chinese) [2] XIAO L, LI X, GONG D, et al. Journal of Instrumentation, 2016, 11: C02013. doi: 10.1088/1748-0221/11/02/C02013 [3] MOREIRA P, BARON S, BONACINI S, et al. Journal of Instrumentation, 2010, 5: C11022. doi: 10.1088/1748-0221/5/11/C11022 [4] GUETTOUCHE N, BARON S, BIEREIGEL S, et al. Journal of Instrumentation, 2022, 17: C03040(17). doi: 10.1088/1748-0221/17/03/C03040 [5] ZHANG L, CRUDA E M, CHAO C P, et al. Journal of Instrumentation, 2020, 17: C03011. doi: 10.1088/1748-0221/17/03/C03011 [6] 张健忠, 常昌远. 电子与封装, 2007, 7(10): 33. doi: 10.3969/j.issn.1681-1070.2007.10.008 ZHANG Jianzhong, CHANG Changyuan. Electronics & Packaging, 2007, 7(10): 33. (in Chinese) doi: 10.3969/j.issn.1681-1070.2007.10.008 [7] 刘玮, 肖磊, 杨莲兴. 固体电子学研究与进展, 2009, 29(1): 100. doi: 10.3969/j.issn.1000-3819.2009.01.022 LIU Wei, XIAO Lei, YANG Lianxing. Reseerch & Progress of SSE, 2009, 29(1): 100. (in Chinese) doi: 10.3969/j.issn.1000-3819.2009.01.022 [8] 韦龙飞. 多速率SerDes发送模块芯片设计与验证[D]. 成都: 电子科技大学, 2013(6): 15. WEI Longfei. Design and Verification of a Multi-rate Serdes Transmitter[D]. Chengdu:University of Electronic Science and Technology of China, 2013(6): 15. (in Chinese) [9] FUKAISHI M, NAKAMURA K, HEIUCHI H, et al. IEEE Journal of Solid-State Circuits, 2000, 35(11): 1611. doi: 10.1109/4.881206 [10] 孟辰星, 黄光明, 郭迪. 电子与封装, 2020, 20(2): 020303. MENG Chenxing, HUANG Guangming, GUO Di. Electronics & Packaging, 2020, 20(2): 020303. (in Chinese) [11] 伍得阳. 低抖动时钟占空比校准电路的研究与设计[D]. 上海: 复旦大学, 2013(4): 1. WU Deyang. Research and Design of Low Jitter Clock Duty Cycle Calibration Circuit[D]. Shanghai:Fudan University, 2013(4): 1. (in Chinese)
基于国产工艺的高速并串转换电路设计
doi: 10.11804/NuclPhysRev.39.2021078
- 收稿日期: 2021-10-15
- 修回日期: 2021-12-07
- 网络出版日期: 2022-11-09
- 刊出日期: 2022-09-20
摘要: 面向全国产化工艺的5 Gbps SerDes(Serializer/DESerializer,串化器/解串器)芯片的需求,设计了其中的20:1 Serializer(并串转换电路)。该并串转换电路基于国产GSMC 130 nm CMOS工艺设计,其内部电路结构设计采用了一级5:1模块和两级2:1模块级联方式,并由多相时钟发生器和分频器提供相应的时钟信号,将20路250 Mbps并行数据转换成1路5 Gbps的高速串行数据进行传输。在温度−40~100 °C、全工艺角环境、电路工作电压在1.08~1.32 V 的条件下,后仿真结果均显示该电路功能正确,能输出完整清晰的5 Gbps数据眼图, 满足设计需求。 其中在27 °C、TT Corner(典型值工艺角)、1.2 V工作电压条件下仿真结果表明该并串转换电路整体总功耗为39.12 mW、总抖动为8.34 ps、输出电压满摆幅为800 mV。
English Abstract
Design of a High-speed Serializer with a Domestic CMOS Process
- Received Date: 2021-10-15
- Rev Recd Date: 2021-12-07
- Available Online: 2022-11-09
- Publish Date: 2022-09-20
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Keywords:
- parallel and serial conversion circuit /
- high-speed data transmission /
- demostic CMOS process /
- SerDes
Abstract: This paper designs a 20:1 Serializer for a 5 Gbps SerDes (Serializer/DESerializer) ASIC fabricated using China's domestic GSMC 130 nm CMOS process. This Serializer converts the 20-bit 250 Mbps parallel data into 1-bit 5Gbps serial data. It consists of one stage of 5:1 conversion module and two stages of 2:1 conversion module. The clocks are provided by a multi-phase clock generator and a frequency divider. Post-simulations with all process corners, the temperature is from −40 °C to 100 °C and supply voltage is from 1.08 to 1.32 Volt, show this Serializer functions correctly and can generate a clear eye diagram at 5 Gbps, which fulfills the design requirements. Mainly, simulation with the typical process corner, the temperature at 27 °C, and supply voltage at 1.2 Volt show that the total power dissipation is 39.12 mW, the total jitter is 8.34 ps, and the output voltage rail-to-rail is 800 mV.
引用本文: | 屈祥如, 周威, 牛晓阳, 赵承心. 基于国产工艺的高速并串转换电路设计[J]. 原子核物理评论, 2022, 39(3): 343-351. doi: 10.11804/NuclPhysRev.39.2021078 |
Citation: | Xiangru QU, Wei ZHOU, Xiaoyang NIU, Chengxin ZHAO. Design of a High-speed Serializer with a Domestic CMOS Process[J]. Nuclear Physics Review, 2022, 39(3): 343-351. doi: 10.11804/NuclPhysRev.39.2021078 |